The VSC8242 is a dual port clock and data recovery (CDR) device with on-chip adaptive electronic dispersion compensation (EDC). It is intended for use as a versatile CDR and retimer for all 10 Gbps Ethernet reaches compliant with IEEE 802.3ae and IEEE 802.3aq physical layer specifications. The device operates at 9.9 Gbps to 11.3 Gbps, as well as 1.25 Gbps, complying to the legacy 1 Gbps Ethernet standards.

The VSC8242 receive path input receiver is designed to compensate for loss of optical system performance or margin under intersymbol interference caused by propagation through multi-mode fiber (MMF) using a sophisticated FFE-DFE technology. The equalizer compensates for optical modal dispersion as well as additional intersymbol interference(ISI) caused by the propagation of the received signal through the PCB interconnect, connectors, vias, and stubs as found on line cards and backplanes. An embedded microcontroller with on-board RAM allows an internal algorithm to adapt the VSC8242 receiver in a manner transparent to the end-user to obtain better than 10–12 BER, compliant with the IEEE 802.3aq standard transmit and channel conditions. The input receiver output is retimed with a CDR phase-locked-loop (PLL) followed by a data output driver. The transmit path consists of an input receiver with an integrated equalization (EQ) circuit designed for copper trace equalization, followed by a CDR PLL, and an SFI-compliant output driver with pre-emphasis.

A single-ended, differential, LVPECL-compatible (optional single-ended TTL) reference clock is used as a frequency reference input for the receive and transmit CDRs. In 10 Gbps mode, VSC8242 can accept either a divide-by-64 (default) or 66 reference clock. In 1.25 Gbps mode, a divide-by-64 reference clock is accepted. Two loopback modes allow recovered receive path input data to be output on the transmit path output pins (line-side loopback), and likewise recovered transmit input data output on the receive path output pins (host-side loopback). The loopback circuitry can be disabled in normal mode for power savings.