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| Home > Featured Products > Volume 5 - IDT High Performance FIFOs |
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| The Industry’s Widest Range Of High-Performance Fifo Products |
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| First-In First-Out (FIFO) ICs can efficiently solve
inter-chip communications protocol problems. |
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Problems such as rate matching, buffering and bus-width matching. IDT offers the industry’s most extensive product portfolio of these versatile standard devices. The wide range of available densities, organizations, speeds, operating characteristics and price points among the five distinct product lines makes it easy to find just the right FIFOs for any set of design requirements.
For networking and wired or wireless telecommunications equipment, data acquisition systems, medical imaging products and many other applications, there are more than 350 synchronous, asynchronous and bi-directional devices to choose from in the TeraSync™, TeraSync™ DDR/SDR, SuperSync™ and bidirectional FIFO families. Optimize solution cost, increase system throughput, save board space, cut design time. Compared with “design from scratch” approaches that involve creating FPGAs or ASICs, easy-to-use IDT FIFOs offer a more sensible way to perform buffering and width/rate matching tasks. At minimum, these readily available, off-the-shelf standard products can reduce the complexity, cost and package size of the semi-custom or custom chips, while also reducing NRE costs and other engineering expenses. See Figures A and B on next page. Our FIFOs shorten time-to-market by conserving valuable time within the implementation and verification phases of the product design cycle. Moreover, they increase design flexibility because they cover a broad span of operating frequencies. By plugging in faster, pin-compatible FIFOs, it’s possible to increase system performance levels without changing the system architecture. |
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| Superior solutions— now and in the future as well as maintaining and enhancing our leadership position in the FIFO market is an ongoing IDT goal. As we strive to meet the current and future needs of the markets we serve, we make product improvements and introduce innovative new products, constantly building on more than 20 years of experience. For example, to help system engineers meet the challenges of rising transmission rates, IDT is pioneering high-speed, cost-effective FIFO products that combine advanced storage technologies with inventive logic architectures. |
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TeraSync™
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High speed/high density |
TeraSync™
DDR/SDR |
Very high-speed DDR/SDR |
| SuperSync™ |
SuperSync™
World’s most popular FIFO line |
| Bi-Directional |
Bi-Directional, bus-buffering |
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| TeraSync™ FIFOs from IDT come in a wide range of densities and bus widths, and include devices with up to 9 Mb of memory—the industry’s highest density. They provide unmatched performance and I/O flexibility. Built on the latest process technology, the FIFOs in the TeraSync family operate at a 2.5 V core voltage and achieve the extremely low power consumption needed to fit into tight power budgets. |
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- Up to 18 Mb densities
- 9-, 18-, 36- and 72-bit configurations with pin-compatible
upgrades over a wide range of densities
- 225 MHz high-speed operation
- Low-power 2.5 V operation
- Mark and re-transmit function
- Echo clock output and read enable
- BGA packaging with JTAG feature
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- Frequency: 0 to 225 MHz
- I/O levels: LVTTL, HSTL or eHSTL
- Bus width: 9-, 18-, 36- or 72-bits
- Timing modes: clocked or asynchronous interface
- Write/read chip select:
For additional power savings
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| The IDT TeraSync DDR/SDR family comprises FIFOs with double data rate (DDR) capabilities—an industry first. The input and output ports of these fast devices can be configured independently to operate either in single-data-rate (SDR) or DDR mode. As a result, these FIFOs deliver data rates up to 10 Gbps, twice the bandwidth that would otherwise be available. Other independently selectable input and output options, such as voltage levels, bus widths and frequencies, further boost design flexibility, allowing engineers to save time and cost while increasing system performance. |
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- High-speed operation up to 250 MHz
- Selectable independent DDR/SDR operation, up to 10 Gbps
- Low-power 2.5 V operation
- Extended bus interfaces with 40-, 20-, and 10-bit options
- Densities up to 5 Mb
- Echo clock output and read enable
- BGA packaging with JTAG feature
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- Data-Rate: DDR/SDR
- Frequency: 0 to 250 MHz
- I/O Levels: LVTTL, HSTL or eHSTL
- Bus Width: 10-, 20- or 40-bits
- Write/read chip select: for additional power savings
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| High-density |
Delivers industry’s deepest FIFO; enables buffering of largest amounts of data on a single chip at an effective price point |
| High-speed operation |
Provides requisite line-speed performance. Synchronous interface with independent read and write clocks enable frequency matching between different clock domains |
| Echo clock output |
Supports high-speed operation by controlling data phase and timing relationship |
| Port-selectable double data rate |
Offers the industry’s first and only DDR FIFO. Optimizes data rate without increasing the speed or width of the device |
| Port-selectable timing modes |
Interfaces to devices that operate either synchronous (clocked) or asynchronous (pulse triggered), e.g., DSPs |
| Port-selectable I/O levels (HSTL/LVTTL) |
Enhances high-speed operation with the flexibility to interface with various device voltage operation levels |
| Various bus widths and port selectable bus-width matching |
Supports extra bits for x40, x20, and x10 configurations that provide byte and packet boundaries to denote valid bytes and perform packet delineation. Bus-width matching enables seamless interface between systems implemented at different bus widths |
| Mark and re-transmit |
Sends data from a marked location for error correction or system debugging |
| 5 flag outputs |
Provides empty, Half Full, Full, programmable Almost Empty and Almost Full flags to signal FIFO status |
| Low power consumption |
Offers extremely low power consumption at high performance through low core voltage and low current consumption. Synchronous chip enables (WCS, RCS) for additional power savings |
| Flexible expansion |
Enables seamless depth and width expansion through cascading of multiple FIFOs. first-word-fall-through (FWFT) mode to support low first word latency and glueless depth expansion |
| BGA packaging plus JTAG |
Is IEEE 1149.1 compliant. Small package options plus debug and test capabilities for optimized manufacturing and board yields |
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