The flexible, cost-effective multi-ports deliver access times as fast as 55 ns and data rates of 800 Mbps per port to clear out internal data flow bottlenecks. They provide maximum functionality while taking up minimum board space, with packages as small as 6mm x 6mm.

The IDT multi-ports have a 1.8V core voltage; and are available in configurations up to 32K x 16, and synchronous and asynchronous operation. They reduce operating and standby currents by up to 95 percent compared to traditional dual-ports. Operating current is only 15 mA (typ.) and standby current is just 2μA (typ.)
to help extend talk and standby times.

The architecture of IDT low-power multi-ports enables modular, reusable handset designs that can quickly be optimized to address different market requirements. The devices use a standard SRAM interface and support multiple voltage configurations, so existing application or baseband subsystems can be mixed and matched with minimal design effort, saving development time. These features help maximize the returns on system engineering investments, while also significantly shortening new-product design cycles.

The latest IDT low-power dual-port is a synchronous device with low pin count. This low-power, low pin count device offers an address/data multiplexed (ADM) interface to achieve a reduced pin count. The device is specifically designed to allow direct connection with several families of application processors, as well as processors for handsets and mobile applications that make use of an ADM interface. In addition, since the low-power, low pin count dual port can provide performance up to 800 Mbps per port throughput, it is the industry’s fastest low-power dual-port available.

The multi-ports’ innovative input/output circuitry can be used to implement higher levels of handset functionality. The devices’ Input Read and Output Drive registers enable the processors in a system to read the state of two external binary input devices (LEDs, DIP switches, etc.) and drive up to five external binary input devices, using only the standard memory interface of the multi-port. This allows the processors’ GPIO pins to be used for other purposes, facilitating extra or enhanced handset features that gain advantages in competitive markets.