| |
| Board
Features: |
| • |
XC2C256
PQ208C Xilinx CoolRunner-II CPLD: |
| |
DualEDGE
triggered registers |
| |
Clock
divider (÷ 2,4,6,8,10,12,14,16) |
| |
CoolCLOCK |
| |
Multiple
global clocks with phase selection per macrocell |
| |
Multiple
global output enables |
| |
Global
set/ reset |
| |
SSTL2-1,
SSTL3-1, and HSTL-1 |
| • |
64X16
High Speed SRAM: ISSI62LV6416 l |
| • |
1Mbit
Serial Paged Flash: SPI Interface |
| • |
16
Kbit EEPROM: I² C Interface |
| • |
JTAG
Cable IV & III support |
| • |
8
Position DIP Switch |
| • |
4
Push Buttons |
| • |
4
Digit -7 Segment LCD Display |
| • |
8
Status LED's |
| • |
5V,
3.3V and 3.3V -1.8V selectable LDO's |
| • |
35
Test Point Headers: 3.3V
Tolerant |
| • |
35
Test Point Headers: 5V
Tolerant |
| • |
XC9572XL-7TQ100
Xilinx CPLD |
| |
Provides
Interface with external Parallel Port |
| |
Provides
Interface with 5V tolerant Test Point Headers |
| |
Provides
additional programmable logic resources |
| |
Provides
5V tolerant prototyping area |
| • |
20
MHz Clock Oscillator: Available 2nd Oscillator Socket |
| • |
10X15
Prototyping area |
| • |
1
-RS232 Interface: DB9 |
| • |
1
-Parallel Port Interface: DB25 |