What is a RealDigital CPLD?

A CPLD is a combination of a fully programmable AND/OR array and a bank of macrocells. The AND/OR array is reprogrammable and can perform a multitude of logic functions. Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths.

Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. This performance boost came at the cost of very high current requirements. CoolRunner-II RealDigital CPLDs, created by Xilinx, use an innovative all-digital core to achieve the same levels of performance at ultra-low power requirements. This allows designers to use the same CPLD architecture for both high-performance and low-power designs.

The removal of analog sense amplifiers also makes the architecture scaleable, allowing for aggressive cost reduction and feature enhancement with each successive process generation.

Why use a CPLD?

CPLDs perform a variety of useful functions in systems design due to their unique capabilities.

• Reprogrammable - Change your design instantly for no cost as many times as you like, build reconfigurable systems, fix ASIC bugs, upgrade system functions anytime from anywhere; Saves time, lowers cost, simplifies design.
• Simple and easy to use - Designing with CPLDs is simple and easy, fits easily into existing design flow; Saves time, lowers cost, simplifies design.
• Low cost - Reprogram to fix system bugs, low unit cost, replace TTL and ASSPs to reduce board components and improve reliability; lowers design cost, lowers system cost, lowers maintenance cost.
• Nonvolatile - Programming kept on power down, CPLD functions available instantly on system power up, almost impossible to steal stored design; Improves security, simplifies design.

Why choose a Xilinx CPLD?

As the market leader in programmable logic solutions, Xilinx provides a total solution to a designer's CPLD needs:

• Advanced Silicon - Cost-optimized chip design, high performance, low power operation, the widest range of packaging, advanced system features, highest I/O per macrocell counts.
• Free, powerful design tools - The ISE WebPACK design tools offer the most complete, easy-to-use desktop software solution for developing any Xilinx CPLD.
• Everything else - Free reference designs and application notes, a design kit to get you started, a vast network of distributors, sales representatives, field application engineers, and in-house technical support, and a wide array of online technical documentation.