Introduction to Serial IO

Course Description

This full day workshop introduces the GTP RocketIO™ transceiver available in the new Virtex™-5 LXT family of Platform FPGAs. This class covers the basic architecture of the GTP_DUAL primitive and provides a basic explanation of functional blocks and their roles. Attendees will use CORE Generator™ and Chipscope™ Pro to generate, implement, download and test a GTP design.

Workshop Agenda

•	Line Card Overview - Power and Clocking Solutions
•	Introduction to Virtex 5
•	Virtex 5 GTP-GTX Overview
•	Intro to Chipscope Pro and the Serial IO toolkit
•	Lunch - Renesas Product Overview and Demo
•	Xilinx Gigabit Transceiver Lab: LX50T GTP Ports

Date:
May 22, 2008
Location:
Eldorado Hotel & Casino
Time:
9AM to 4PM
Address:
345 North Virginia St.
Reno, NV 89501

Contact:
John Parkhurst
Email:
jparkhurst@nuhorizons.com

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