Introduction to Serial IO

Course Description

This half day workshop introduces the GTP RocketIO™ transceiver available in the new Virtex™-5 LXT family of Platform FPGAs. This class covers the basic architecture of the GTP_DUAL primitive and provides a basic explanation of functional blocks and their roles. Attendees will use CORE Generator™ and Chipscope™ Pro to generate, implement, download and test a GTP design.

Course Outline

•	Introduction
•	Virtex 5 LXT overview
•	GTP introduction
•	Lab 1
•	Intro to Chipscope Pro and the Serial IO toolkit
•	Lab 2

Short presentation on related analog/power products from Linear Technology

Prerequisite -- Attendees should have a familiarity with the ISE tool flow and basic HDL knowledge


Click on the dates / cities listed below to register online and to view locations
North America

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