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Signal Integrity Seminar
 
 
Course Description:

Vitesse, the worldwide leader in high-speed semiconductor ICs for Networking and Storage equipment, invites you to the upcoming Signal Integrity workshop.

The technology seminar has been crafted to educate design engineers & system architects on best practices to preserve signal integrity when designing next generation Networking & Storage systems.

Vitesse technology experts will demonstrate how to shorten product development cycles using proven, high-speed design techniques to maintain signal integrity through printed circuit boards, backplanes and copper interconnect media. The Signal Integrity session provides engineers with proven guidelines, tools, techniques, demos, and products needed to address signal integrity issues in next generation systems. Topics include an overview of issues impacting signal integrity as signals move toward and beyond the 1 0Gb/s speeds. Also covered in this workshop will be in depth tutorials on Vitesse's latest 10G/EDC and patented VScope embedded waveform viewing technology.

 

Agenda:

  • Signal Integrity issues intro
  • Board design considerations
  • IC Shopping Guide
  • Advanced EQ - 10G/EDC
  • VScope embedded waveform viewing technology
  • Vitesse Signal Integrity solutions
 
 
 
 

Date: February 5, 2009
Location: Santa Clara, CA
Time: 8:30 am – 12:00 noon
(Refreshments provided)

Address:
Santa Clara Hilton
4949 Great America Parkway
Santa Clara, CA 95054
(408) 330-0001     
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